Job description

Cientra is Looking for a Lead Verification Engineer in Austin, Texas

Minimum Qualifications:

• BSEE/MSEE/BSCompE/MSCompE with 10+ years of industry experience
• At least 3+ years of UVM experience (so this implies 3+ years of SystemVerilog as well)
• Deep understanding of coverage, constrained-random, transaction level
• Experience with Verdi/VCS is a must
• Experience with test plan documentation
• Familiarity with Python3/Bash/Tcl scripting is a must
• Experience with debugging simulation failures to guide digital design
• Experience with fixed-point arithmetic
• Experience with performance analysis and performance characterization a plus.
• Experience with using Hierarchical Verification Plan is a plus.
• Experienced with a full ASIC/SOC tape out from beginning to end
• Experience with video processing or graphics pipelines is a plus
• Experience with floating-point arithmetic in addition to fixed-point arithmetic
• Experience Graphics Verification experience is an added advantage

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Interested candidates apply through the below link. Apply before the link expires.
( Select Apply Without Registration )

Note: Only shortlisted candidates will receive the call letter for further rounds.