Hiring Freshers for Design Engineer Role at Xilinx | Hyderabad

  • Hyderabad
  • Private
  • As per Company Standards
  • Deadline: Feb 28, 2021
Job information

Category

Fresher

Open Positions

10

Experience

0 to 1 Year

Work shift

Day

Employment Status

Permanent

Deadline

Feb 28, 2021

Job description

Xilinx hiring Graduate freshers, who can are individual to be creative, team-oriented, technology savvy, able to design complex RTL blocks given a high-level microarchitecture and take complete responsibility for quality delivery of the designs.

Hiring Freshers for Design Engineer Role at Xilinx | Hyderabad

Job Position: Design Engineer

Qualification:  Bachelors or Masters in Computer or Electrical/Electronics engineering

Job Summary:

This exciting position in the Xilinx Data Center Storage IP & Solutions Engineering group as the storage domain designer will provide the individual with an opportunity to get exposed to next-generation data centre storage IP offerings. Join us in delivering innovative IP solutions as we embark on our journey in providing world-class storage solutions at more than 100Gbps line rate for Xilinx All Programmable FPGA platforms

As a Design Engineer, you will work as part of a team responsible for all phases of product development from definition to execution and Productization. Design engineers get exposed to all aspects of a technical project including u-Architecture development for individual IPs or IP subsystems, leading cross-functional IP teams from front-end development through Productization

This position requires the individual to be creative, team-oriented, technology savvy, able to design complex RTL blocks given a high-level microarchitecture and take complete responsibility for quality delivery of the designs

Requirements:

  • Bachelors or Masters in Computer or Electrical/Electronics engineering.
  • Strong academic background.
  • A minimum of 2 years of relevant experience is required.
  • Strong logic design concepts and computer design.
  • Expertise in Verilog, VHDL and exposure to industry simulators.
  • Expertise in front end RTL design flow steps like lint, CDC, STA etc.
  • Exposure in IP design

Interested candidates apply through the below link. Apply before the link expires.


Interested candidates apply through the below link. Apply before the link expires.
( Select Apply Without Registration )

Note: Only shortlisted candidates will receive the call letter for further rounds.

Apply Now
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